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| CR14 Low Cost ISO14443 type-B Contactless Coupler Chip with Anti-Collision and CRC Management Features summary Single 5V 500mV Supply Voltage SO16N package Contactless Communication - ISO14443 type-B protocol - 13.56MHz Carrier Frequency using an External Oscillator - 106 Kbit/s Data Rate - 36 Byte Input/Output Frame Register - Supports Frame Answer with/without SOF/ EOF - CRC Generation and Check - Automated ST Anti-Collision Exchange IC Communication - Two Wire IC Serial Interface - Supports 400kHz Protocol - 3 Chip Enable Pins - Up to 8 CR14 Connected on the Same Bus 16 1 SO16 (MQ) 150 mils width December 2005 Rev 1 1/46 www.st.com 1 CR14 Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Oscillator (OSC1, OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Antenna Output Driver (RFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Antenna Input Filter (RFIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transmitter Reference Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply (VCC, GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 CR14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 3.3 Parameter Register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Slot Marker Register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 CR14 IC protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 4.2 4.3 4.4 4.5 4.6 4.7 IC Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IC Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IC Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IC Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IC Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CR14 IC Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CR14 IC Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Applying the IC protocol to the CR14 registers . . . . . . . . . . . . . . . . . . . . 22 5.1 5.2 5.3 5.4 IC Parameter Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IC Input/Output Frame Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IC Slot Marker Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Addresses above Location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/46 CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer . . . . . . . . . . . . . . 26 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Output RF Data Transfer from the CR14 to the PICC (Request Frame) . . . . 26 Transmission Format of Request Frame Characters . . . . . . . . . . . . . . . . . . 27 Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Input RF Data Transfer from the PICC to the CR14 (Answer Frame) . . . . . . 28 Transmission Format of Answer Frame Characters . . . . . . . . . . . . . . . . . . . 29 Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Tag access using the CR14 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 7.2 Standard TAG Command Access Description . . . . . . . . . . . . . . . . . . . . . . . 31 Anti-Collision TAG Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 9 10 11 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Appendix A ISO14443 type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3/46 CR14 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CR14 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Parameter Register Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input/Output Frame Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slot Marker Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CR14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IC AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 IC Input Parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 IC DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IC AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RFOUT AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 RFIN AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4/46 CR14 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CR14 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Maximum RL Value versus Bus Capacitance (CBUS) for an IC Bus . . . . . . . . . . . . . . . . . 11 IC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CR14 IC Write Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IC Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CR14 IC Read Modes Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Host-to-CR14 Transfer: IC Write to Parameter Register . . . . . . . . . . . . . . . . . . . . . . . . . 22 CR14-to-Host Transfer: IC Random Address Read from Parameter Register . . . . . . . . . 22 CR14-to-Host Transfer: IC Current Address Read from Parameter Register . . . . . . . . . . 22 Host-to-CR14 Transfer: IC Write to Input/Output Frame Register for ISO14443B . . . . . . 23 CR14-to-Host Transfer: IC Random Address Read from Input/Output Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CR14-to-Host Transfer: IC Current Address Read from I/O Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Host-to-CR14 Transfer: IC Write to Slot Marker Register . . . . . . . . . . . . . . . . . . . . . . . . . 24 CR14-to-Host Transfer: IC Random Address Read from Slot Marker Register . . . . . . . . 25 CR14-to-Host Transfer: IC Current Address Read from Slot Marker Register . . . . . . . . . 25 Wave Transmitted using ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CR14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Wave Received using BPSK Sub-carrier Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Example of a Complete Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CRC Transmission Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Standard TAG Command: Request Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 31 Standard TAG Command: Answer Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Standard TAG Command: Complete TAG Access Description . . . . . . . . . . . . . . . . . . . . . 32 Anti-Collision ST short range memory Sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Anti-Collision ST short range memory Sequence Continued . . . . . . . . . . . . . . . . . . . . . . . 34 IC AC Testing I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 IC AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CR14 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 42 5/46 1 Summary description CR14 1 Summary description The CR14 is a contactless coupler that is compliant with the short range ISO14443 type-B standard. It is controlled using the two wire IC bus. The CR14 generates a 13.56MHz signal on an external antenna. Transmitted data are modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna, using Bit Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is 10% modulated. The Data transfer rate between the CR14 and the PICC is 106 Kbit/s in both transmission and reception modes. The CR14 follows the ISO14443 type-B recommendation for Radio frequency power and signal interface. The CR14 is specifically designed for short range applications that need disposable and reusable products. The CR14 includes an automated anti-collision mechanism that allows it to detect and select any ST short range memories that are present at the same time within its range. The anticollision mechanism is based on the STMicroelectronics probabilistic scanning method. The CR14 provides a complete analog interface, compliant with the ISO14443 type-B recommendations for Radio-Frequency power and signal interfacing. With it, any ISO14443 type-B PICC products can be powered and have their data transmission controlled via a simple antenna. The CR14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS technology. The CR14 is organized as 4 different blocks (see Figure 2): The IC bus controller. It handles the serial connection with the application host. It is compliant with the 400kHz IC bus specification, and controls the read/write access to all the CR14 registers. The RAM buffer. It is bi-directional. . It stores all the request frame Bytes to be transmitted to the PICC, and all the received Bytes sent by the PICC on the answer frame. The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for outgoing data. The receiver. It demodulates the signal generated on the antenna by the load variation of the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift keying) sub-carrier decoder. The CR14 is designed to be connected to a digital host (Microcontroller or ASIC). This host has to manage the entire communication protocol in both transmit and receive modes, through the IC serial bus. 6/46 CR14 Figure 1. Logic Diagram VCC VREF 1 Summary description OSC1 RFOUT OSC2 SCL SDA E0 E1 E2 CR14 Antenna RFIN GND GND_RF ai12059 Table 1. RFOUT RFIN OSC1 OSC2 E0, E1, E2 SDA SCL VCC GND VREF GND_RF Signal Names Antenna Output Driver Antenna Input Filter Oscillator Input Oscillator Output Chip Enable Inputs IC Bi-Directional Data IC Clock Power Supply Ground Transmitter Reference Voltage Ground for RF circuitry 7/46 1 Summary description CR14 Logic Block Diagram VCC CR14 Transmitter OSC1 IC Bus Controller RFOUT OSC2 Antenna VREF Figure 2. RAM Buffer Receiver SCL SDA E0 E1 E2 RFIN GND GND_RF AI12060 Figure 3. SO Pin Connections SO16 VREF RFIN E0 E1 E2 GND_RF GND GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RFOUT GND_RF OSC1 OSC2 GND SCL SDA AI10911 8/46 CR14 2 Signal description 2 Signal description See Figure 1: Logic Diagram, and Table 1: Signal Names, for an overview of the signals connected to this device. 2.1 Oscillator (OSC1, OSC2) The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The OSC1 pin is the input pin, the OSC2 is the output pin. For correct operation of the CR14, it is required to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external clock is used, it must be connected to OSC1 and OSC2 must be left open. 2.2 Antenna Output Driver (RFOUT) The Antenna Output Driver pin, RFOUT, generates the modulated 13.56MHz signal on the antenna. Care must be taken as it will not withstand a short-circuit. RFOUT has to be connected to the antenna circuitry as shown in Figure 4: CR14 Application Schematic The LRC antenna circuitry must be connected across the RFOUT pin and GND. 2.3 Antenna Input Filter (RFIN) The antenna input filter of the CR14, RFIN, has to be connected to the external antenna through an adapter circuit, as shown in Figure 4. The input filter demodulates the signal generated on the antenna by the load variation of the PICC. The resulting signal is then decoded by the 847kHz BPSK decoder. 2.4 Transmitter Reference Voltage (VREF) The Transmitter Reference Voltage input, VREF, provides a reference voltage used by the output driver for ASK modulation. The Transmitter Reference Voltage input should be connected to an external capacitor, as shown in Figure 4. 2.5 Serial Clock (SCL) The SCL input pin is used to strobe all IC data in and out of the CR14. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. 9/46 2 Signal description CR14 2.6 Serial Data (SDA) The SDA signal is bi-directional. It is used to transfer IC data in and out of the CR14. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial data (SDA) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). 2.7 Chip Enable (E0, E1, E2) The Chip Enable inputs E0, E1, E2 are used to set and reset the value on the three least significant bits (b3, b2, b1) of the 7-bit IC Device Select Code. They are used for hardwired addressing, allowing up to eight CR14 devices to be addressed on the same IC bus. These inputs may be driven dynamically or tied to VCC or GND to establish the Device Select Code (note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL compatible). When left open, E0, E1 and E2 are internally read at the logic level 0 due to the internal pulldown resistors connected to each inputs. 2.8 Power Supply (VCC, GND, GND_RF) Power is supplied to the CR14 using the VCC, GND and GND_RF pins. VCC is the Power Supply pin that supplies the power (+5V) for all CR14 operations. The GND and GND_RF pins are ground connections. They must be connected together. Decoupling capacitors should be connected between the VCC Supply Voltage pin, the GND Ground pin and the GND_REF Ground pin to filter the power line, as shown in Figure 4. Figure 4. CR14 Application Schematic D1 1N4148 (OPTIONAL) C6VCC VCC OPT OPT R1 R3 E0 0R R2 R4 WURTH 742-792-042U1 FL7 1 VREF VCC 2 R5 RFIN RFOUT 22nF50V 3 E0 GND_RF 4 E1 OSC1 5 E2 OSC2 6 E2 GND_RF GND 7 0R GND SCL 8 GND SDA R6 CR14 OPT C3 C1 7pF50V 16 15 14 13 12 11 10 9 C8' 8pF50V C8 100pF50V 100nF50V C5 10pF50V R8 0R ANT1 E1 0R X1 13.56MHz C7 C7' 120pF50V 33pF50V C2 7pF50V R7 0R J1 4 3 2 1 FL5 0R FL4 FL6 0R 0R VCC + C4 22uF 10V SDASCL ANT2 AI12061 10/46 CR14 Figure 5. 20 Maximum RP value (k) 16 2 Signal description Maximum RL Value versus Bus Capacitance (CBUS) for an IC Bus VCC RL 12 8 4 0 10 100 CBUS (pF) 1000 MASTER fc = 100kHz fc = 400kHz SDA SCL RL CBUS CBUS AI01665 11/46 3 CR14 registers CR14 3 CR14 registers The CR14 chip coupler contains six volatile registers. It is entirely controlled, at both digital and analog level, using the three registers listed below and shown in Table 2: Parameter Register Input/Output Frame Register Slot Marker Register The other 3 registers are located at addresses 02h, 04h and 05h. They are "ST Reserved", and must not be used in end-user applications. In the IC protocol, all data Bytes are transmitted Most Significant Byte first, with each Byte transmitted Most significant bit first. Table 2. Address 00h Parameter Register CR14 Control Registers Length 1 Byte R Input/output Frame Register W 36 Bytes R W Read parameter register Store and send request frame to the PICC. Wait for PICC answer frame Transfer PICC answered frame data to Host ST Reserved, must not be used. R W Launch the automated anti-collision process from Slot_0 to Slot_15 Return data FFh Access W Purpose Set parameter register 01h 02h ST Reserved NA 03h Slot Marker Register 1 Byte R 04h 05h ST Reserved ST Reserved NA NA R and W ST Reserved. Must not be used R and W ST Reserved. Must not be used 12/46 CR14 3 CR14 registers 3.1 Parameter Register (00h) The Parameter Register is an 8-bit volatile register used to configure the CR14, and thus, to customize the circuit behavior. The Parameter Register is located at the IC address 00h and it is accessible in IC Read and Write modes. Its default value, 00h, puts the CR14 in standard ISO14443 type-B configuration. Table 3. Bit b0 b1 b2 Parameter Register Bits Description Control Value 0 Description ISO14443 type-B frame management RFU(1) Not used Answer PICC Frames are delimited by SOF and EOF Answer PICC Frames do not provide SOF and EOF delimiters 10% ASK modulation depth mode RFU 13.56MHz carrier on RF OUT is OFF 13.56MHz carrier on RF OUT is ON Frame Standard 1 RFU Answer Frame Format 1 0 ASK Modulation Depth 1 0 Carrier Frequency 1 tWDG 0 0 b3 b4 b5 b6 b7 Answer delay watchdog RFU b5=0, b6=0: Watchdog time-out = 500s to be used for read b5=0, b6=1: Watchdog time-out = 5ms to be used for read b5=1, b6=0: Watchdog time-out = 10ms to be used for write b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings 0 Not used 1. RFU = Reserved for Future Use. 3.2 Input/Output Frame Register (01h) The Input/Output Frame Register is a 36-Byte buffer that is accessed serially from Byte 0 through to Byte 35 (see Table 4). It is located at the IC address 01h. The Input/Output Frame Register is the buffer in which the CR14 stores the data Bytes of the request frame to be sent to the PICC. It automatically stores the data Bytes of the answer frame received from the PICC. The first Byte (Byte 0) of the Input/Output Frame Register is used to store the frame length for both transmission and reception. When accessed in IC Write mode , the register stores the request frame Bytes that are to be transmitted to the PICC. Byte 0 must be set with the request frame length (in Bytes) and the frame is stored from Byte 1 onwards. At the end of the transmission, the 16-bit CRC is automatically added. After the transmission, the CR14 wait for the PICC to send back an answer frame. When correctly decoded, the PICC answer frame Bytes are stored in the Input/ Output Frame Register from Byte 1 onwards. Byte 0 stores the number of Bytes received from the PICC. When accessed in IC Read mode, the Input/Output Register sends back the last PICC answer frame Bytes, if any, with Byte 0 transmitted first. The 16-bit CRC is not stored, and it is not sent back on the IC bus. 13/46 3 CR14 registers CR14 The Input/Output Frame Register is set to all 00h between transmission and reception. If there is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is set to FFh, and the data Bytes are discarded and not appended in the register. The CR14 Input/Output Frame Register is so designed as to generate all the ST short range memory command frames. It can also generate all standardized ISO14443 type-B command frames like REQB, SLOT-MARKER, ATTRIB, HALT, and get all the answers like ATQB, or answer to ATTRIB. All ISO14443 type-B compliant PICCs can be accessed by the CR14 provided that their data frame exchange is not longer than 35 Bytes in both request and answer. Table 4. Byte 0 Frame Length Input/Output Frame Register Description Byte 1 First data Byte Byte 2 Second data Byte Byte 3 ... Byte 34 Byte 35 Last data Byte <------------- Request and Answer Frame Bytes exchanged on the RF -------------> 00h No Byte transmitted FFh CRC Error xxh Number of transmitted Bytes 3.3 Slot Marker Register (03h) The slot Marker Register is located at the IC address 03h. It is used to trigger an automated anti-collision sequence between the CR14 and any ST short range memory present in the electromagnetic field. With one IC access, the CR14 launches a complete stream of commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame Register (IC address 01h). This automated anti-collision sequence simplifies the host software development and reduces the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision mechanism. When accessed in IC Write mode, the Slot Marker Register starts generating the sequence of anti-collision commands. After each command, the CR14 wait for the ST short range memory answer frame which contains the Chip_ID. The validity of the answer is checked and stored into the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in Table 6). If the answer is correct, the Status Slot Bit is set to `1' and the Chip_ID is stored into the corresponding Slot_Register. If no answer is detected, the Status Slot Bit is set to `0', and the corresponding Slot_Register is set to 00h. If a CRC error is detected, the Status Slot Bit is set to `0', and the corresponding Slot_Register is set to FFh. Each time the Slot Marker Register is accessed in IC Write mode, Byte 0 of the Input/Output Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information, and Bytes 3 to 18 store the corresponding Chip_ID or error code. The Slot Marker Register cannot be accessed in IC Read mode. All the anti-collision data can be accessed by reading the Input/Output Frame Register at the IC address 01h. 14/46 CR14 Table 5. Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte n Byte 17 Byte 18 3 CR14 registers Slot Marker Register Description b7 b6 b5 b4 b3 b2 b1 b0 Number of stored Bytes: fixed to 18 Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Slot_Register 0 = Chip_ID value detected in Slot 0 Slot_Register 1 = Chip_ID value detected in Slot 1 Slot_Register 2 = Chip_ID value detected in Slot 2 Slot_Register 3 = Chip_ID value detected in Slot 3 ..... Slot_Register 14 = Chip_ID value detected in Slot 14 Slot_Register 15 = Chip_ID value detected in Slot 15 Status bit value description: 1: No error detected. The Chip_ID stored in the Slot register is valid. 0: Error detected - Slot register = 00h: No answer frame detected from ST short range memory - Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred 15/46 4 CR14 IC protocol description CR14 4 CR14 IC protocol description The CR14 is compatible with the IC serial bus memory standard, which is a two-wire serial interface that uses a bi-directional data bus and serial clock. The CR14 has a pre-programmed, 4-bit identification code, '1010' (as shown in Table 6), that corresponds to the IC bus definition. With this code and the three Chip Enable inputs (E2, E1, E0) up to eight CR14 devices can be connected to the IC bus, and selected individually. The CR14 behaves as a slave device in the IC protocol, with all CR14 operations synchronized to the serial clock. IC Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by the Device Select Code and by a Read/Write bit (R/W). It is terminated by an acknowledge bit. The Device Select Code consists of seven bits (as shown in Table 6): the Device Code (first four bits) plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and E0, respectively When data is written to the CR14, the device inserts an acknowledge bit (9th bit) after the bus master's 8-bit transmission. When the bus master reads data, it also acknowledges the receipt of the data Byte by inserting an acknowledge bit (9th bit). Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK for Read. The CR14 supports the IC protocol, as summarized in Figure 6. Any device that sends data on to the bus, is defined as a transmitter, and any device that reads the data, as a receiver. The device that controls the data transfer is known as the master, and the other, as the slave. A data transfer can only be initiated by the master, which also provides the serial clock for synchronization. The CR14 is always a slave device in all IC communications. All data are transmitted Most Significant Bit (MSB) first. Table 6. Device Select Code Device Code b7 CR14 Select Chip Enable RW b1 E0 b0 RW b6 0 b5 1 b4 0 b3 E2 b2 E1 1 16/46 CR14 4 CR14 IC protocol description 4.1 IC Start Condition START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial Clock, SCL, is stable in the High state. A START condition must precede any data transfer command. The CR14 continuously monitors the SDA and SCL lines for a START condition (except during Radio Frequency data exchanges), and will not respond unless one is sent. 4.2 IC Stop Condition STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial Clock, SCL, is stable in the High state. A STOP condition terminates communications between the CR14 and the bus master. A STOP condition at the end of an IC Read command, after (and only after) a NoACK, forces the CR14 into its stand-by state. A STOP condition at the end of an IC Write command triggers the Radio Frequency data exchange between the CR14 and the PICC. 4.3 IC Acknowledge Bit (ACK) An acknowledge bit is used to indicate a successful data transfer on the IC bus. The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge the receipt of the 8 data bits. 4.4 IC Data Input During data input, the CR14 samples the SDA bus signal on the rising edge of the Serial Clock, SCL. For correct device operation, the SDA signal must be stable during the Low-to-High Serial Clock transition, and the data must change only when the SCL line is Low 17/46 4 CR14 IC protocol description CR14 Figure 6. SCL IC Bus Protocol SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK START CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK STOP CONDITION AI00792 4.5 IC Memory Addressing To start up communication with the CR14, the bus master must initiate a START condition. Then, the bus master sends 8 bits (with the most significant bit first) on the Serial Data line, SDA. These bits consist of the Device Select Code (7 bits) plus a RW bit. According to the IC bus definition, the seven most significant bits of the Device Select Code are the Device Type Identifier. For the CR14, these bits are defined as shown in Table 6. The 8th bit is the Read/Write bit (RW). It is set to `1' for IC Read, and to `0' for IC Write operations. If the data sent by the bus master matches the Device Select Code of a CR14 device, the corresponding device returns an acknowledgment on the SDA bus during the 9th bit time. The CR14 devices whose Device Select Codes do not correspond to the data sent, generate a No-ACK. They deselect themselves from the bus and go into stand-by mode. 18/46 CR14 4 CR14 IC protocol description 4.6 CR14 IC Write Operations The bus master sends a START condition, followed by a Device Select Code and the R/W bit set to '0'. The CR14 that corresponds to the Device Select Code, acknowledges and waits for the bus master to send the Byte address of the register that is to be written to. After receipt of the address, the CR14 returns another ACK, and waits for the bus master to send the data Bytes that are to be written. In the CR14 IC Write mode, the bus master may sends one or more data Bytes depending on the selected register. The CR14 replies with an ACK after each data Byte received. The bus master terminates the transfer by generating a STOP condition. The STOP condition at the end of a Write access to the Input/Output Frame Register causes the Radio Frequency data exchange between the CR14 and the PICC to be started. During the Radio Frequency data exchange, the CR14 disconnects itself from the IC bus. The time (tRFEX) needed to complete the exchange is not fixed as it depends on the PICC command format. To know when the exchange is complete, the bus master uses an ACK polling sequence as shown in Figure 8. It consists of the following: Initial condition: a Radio Frequency data exchange is in progress. Step 1: the master issues a START condition followed by the first Byte of the new instruction (Device Select Code plus R/W bit). Step 2: if the CR14 is busy, no ACK is returned and the master goes back to Step 1. If the CR14 has completed the Radio Frequency data exchange, it responds with an ACK, indicating that it is ready to receive the second part of the next instruction (the first Byte of this instruction being sent during Step 1). CR14 IC Write Mode Sequence START R/W DEV SEL BYTE ADDR DATA 1 DATA 2 DATA 3 DATA N STOP ACK AI12062 Figure 7. BUS Master CR14 WRITE BUS Slave ACK ACK ACK ACK ACK 19/46 4 CR14 IC protocol description CR14 Figure 8. IC Polling Flowchart using ACK Radio Frequency data exchange in progress START Condition DEVICE SELECT CODE with R/W=1 NO ACK returned YES First byte of instruction with R/W = 1 already decoded by the CR14 NO Next operation is addressing the CR14 YES Proceed to READ Operation ReSTART STOP STOP ai12063 20/46 CR14 4 CR14 IC protocol description 4.7 CR14 IC Read Operations To send a Read command, the bus master sends a START condition, followed by a Device Select Code and the R/W bit set to '1'. The CR14 that corresponds to the Device Select Code acknowledges and outputs the first data Byte of the addressed register. To select a specific register, a dummy Write command must first be issued, giving an address Byte but no data Bytes, as shown in the bottom half of Figure 9. This causes the new address to be stored in the internal address pointer, for use by the Read command that immediately follows the dummy Write command. In the IC Read mode, the CR14 may read one or more data Bytes depending on the selected register. The bus master has to generate an ACK after each data Byte to read all the register data in a continuous stream. Only the last data Byte should not be followed by an ACK. The master then terminates the transfer with a STOP condition, as shown in Figure 9. After reading each Byte, the CR14 waits for the master to send an ACK during the 9th bit time. If the master does not return an ACK within this time, the CR14 terminates the data transfer and switches to stand-by mode. Figure 9. CR14 IC Read Modes Sequences R/W DEV SEL ACK ACK ACK ACK NoACK STOP DATA 1 ACK DATA 2 DATA 3 DATA 4 DATA N R/W DEV SEL ADDRESS Re-START R/W DEV SEL ACK ACK NoACK STOP DATA 1 ACK ACK ACK AI12064 IC CURRENT ADDRESS READ START START BUS Master CR14 READ BUS Slave IC RANDOM ADDRESS READ BUS Master CR14 READ BUS Slave DATA 2 DATA N 21/46 5 Applying the IC protocol to the CR14 registers CR14 5 5.1 Applying the IC protocol to the CR14 registers IC Parameter Register Protocol Figure 10 shows how new data is written to the Parameter Register. The new value becomes active after the IC STOP condition. Figure 11 shows how to read the Parameter Register contents. The CR14 sends and re-sends the Parameter Register contents until it receives a NoACK from the IC Host. The CR14 supports the IC Current Address and Random Address Read modes. The Current Address Read mode can be used if the previous command was issued to the register where the Read is to take place. Figure 10. Host-to-CR14 Transfer: IC Write to Parameter Register S T A R T R/W Device Select Code Parameter Register Address Register Byte Value S T O P Bus Master CR14 Write Bus Slave 1 0 1 0XXX 00h data ACK ACK ACK ai12038 Figure 11. CR14-to-Host Transfer: IC Random Address Read from Parameter Register R E S T A R T S T Bus Master A R T CR14 Read Bus Slave R/W Device Select Code Parameter Register Address R/W Device Select Code NoACK S T O P 1 0 1 0XXX 00h 1 0 1 0XXX data Register Byte Value ai12039 ACK ACK ACK Figure 12. CR14-to-Host Transfer: IC Current Address Read from Parameter Register S T A R T R/W Device Select Code NoACK Bus Master S T O P CR14 Read Bus Slave 1 0 1 0XXX data Register Byte Value ai12040 ACK 22/46 CR14 5 Applying the IC protocol to the CR14 registers 5.2 IC Input/Output Frame Register Protocol Figure 13 shows how to store a PICC request frame command of N Bytes into the Input/Output Frame Register. After the IC STOP condition, the request frame is RF transmitted in the ISO14443 type-B format. The CR14 then waits for the PICC answer frame which will also be stored in the Input/ Output Frame Register. The request frame is over-written by the answer frame. Figure 14 shows how to read an N-Byte PICC answer frame. The two CRC Bytes generated by the PICC are not stored. The CR14 continues to output data Bytes until a NoACK has been generated by the IC Host, and received by the CR14. After all 36 Bytes have been output, the CR14 "rolls over", and starts outputting from the start of the Input/Output Frame Register again. The CR14 supports the IC Current Address and Random Address Read modes. The Current Address Read mode can be used if the previous command was issued to the register where the Read is to take place. Figure 13. Host-to-CR14 Transfer: IC Write to Input/Output Frame Register for ISO14443B S T A Bus R Master T CR14 Write Bus Slave R/W Device Select Code 1 0 1 0 XX X Input/Output Register Address 01h Request Frame Length N N PICC Command Code Data 1 PICC Command Parameter Data 2 PICC Command Parameter PICC Command Parameter Data N S T O P ACK ACK ACK ACK ACK ACK ACK ai12041 Figure 14. CR14-to-Host Transfer: IC Random Address Read from Input/Output Frame Register for ISO14443B R/W S Input/Output Device T Register Select Bus A Address Code Master R T CR14 1 0 1 0XXX 01h Read Bus Slave R E S T A R T R/W Device Select Code 1 0 1 0 XXX N Received ACK Frame Length Data1 Answer Frame Data Data 2 Answer Frame Data Answer Frame Data Data N Answer Frame Data ai12042 ACK ACK ACK ACK NoACK S T O P ACK ACK 23/46 5 Applying the IC protocol to the CR14 registers CR14 Figure 15. CR14-to-Host Transfer: IC Current Address Read from I/O Frame Register for ISO14443B S T A R T R/W Device Select Code 1 0 1 0 XX X N Data 1 Data 2 Answer Frame Data Answer Frame Data Data N Answer Frame Data ACK ACK ACK ACK NoACK S T O P Bus Master CR14 Write Bus Slave ACK Received Answer Frame Frame Length Data ai12043 5.3 IC Slot Marker Register Protocol An IC Write command to the Slot Marker Register generates an automated sixteen-command loop (See Figure 16 for a description of the command). All the answers from the ST short range memory devices that are detected, are written in the Input/Output Frame Register. Read from the IC Slot Marker Register is not supported by the CR14. If the IC Host tries to read the Slot Marker Register, the CR14 will return the data value FFh in both Random Address and Current Address Read modes until NoACK is generated by the IC Host. The result of the detection sequence is stored in the Input/Output Frame Register. This Register can be read by the host by using IC Random Address Read. Figure 16. Host-to-CR14 Transfer: IC Write to Slot Marker Register S T A R T R/W Device Select Code Slot Marker Register Address 03h Bus Master S T O P CR14 Write Bus Slave 1 0 1 0XXX ACK ACK ai12044 24/46 CR14 5 Applying the IC protocol to the CR14 registers Figure 17. CR14-to-Host Transfer: IC Random Address Read from Slot Marker Register R E S T A R T Bus Master S T A R T R/W Device Select Code Slot Marker Register Address 00h R/W Device Select Code NoACK S T O P CR14 Read Bus Slave 1 0 1 0XXX 1 0 1 0XXX FFh ACK ACK ACK ai12045 Figure 18. CR14-to-Host Transfer: IC Current Address Read from Slot Marker Register S T A R T R/W Device Select Code NoACK Bus Master S T O P CR14 Read Bus Slave 1 0 1 0XXX FFh ACK ai12047 5.4 Addresses above Location 06h In IC Write mode, when the CR14 receives the 8-bit register address, and the address is above location 06h, the device does not acknowledge (NoACK) and deselects itself from the bus. The Serial Data line, SDA, stays at logic `1' (pull-up resistor), and the IC Host receives a NoACK during the 9th bit time. The SDA line stays High until the STOP condition is issued. In the IC Current and Random Address Read modes, when the CR14 receives the 8-bit register address, and the address is above location 06h, the device does not acknowledge the Device Select Code after the START condition, and deselects itself from the bus. 25/46 6 CR14 ISO14443 type-B Radio Frequency data transfer CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer Output RF Data Transfer from the CR14 to the PICC (Request Frame) The CR14 output buffer is controlled by the 13.56MHz clock signal generated by the external oscillator and by the request frame generator. The CR14 can be directly connected to an external matching circuit to generate a 13.56MHz sinusoidal carrier frequency on its antenna. The current driven into the antenna coil is directly generated by the CR14 RFOUT output driver. If the antenna is correctly tuned, it emits an H-field of a large enough magnitude to power a contactless PICC from a short distance. The energy received on the PICC antenna is converted to a Power Supply Voltage by a regulator, and turned into data bits by the ASK demodulator. The CR14 amplitude modulates the 13.56MHz wave by 10% as represented in Figure 19. The data transfer rate is 106 kbit/s. Figure 19. Wave Transmitted using ASK Modulation 6.1 DATA BIT TRANSMITTED BY THE CR14 10% ASK MODULATION OF THE 13.56MHz WAVE, GENERATED BY THE RFOUT DRIVER 10% ASK MODULATION OF THE 13.56MHz WAVE, GENERATED ON THE CR14 ANTENNA Transfer time for one data bit is 1/106 kHz AI12048 26/46 CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer 6.2 Transmission Format of Request Frame Characters The CR14 transmits characters of 10 bits, with the Least Significant Bit (b0) transmitted first, as shown in Figure 20. Several 10-bit characters, preceded by the Start Of Frame (SOF) and followed by the End Of Frame (EOF), constitute a Request Frame, as shown in Figure 26. A Request Frame includes the SOF, instructions, addresses, data, CRC and the EOF as defined in the ISO14443 type-B. Each bit duration is called an Elementary Time Unit (ETU). One ETU is equal to 9.44s (1/ 106kHz). Figure 20. CR14 Request Frame Character Format b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 1 Start LSB ETU '0' Information Byte MSB Stop '1' ai12049 Table 7. Bit b0 b1 to b8 b9 CR14 Request Frame Character Format Description Start bit used to synchronize the transmission Information Byte (instruction, address or data) Stop bit used to indicate the end of the character b0 = 0 Information Byte is sent Least Significant Bit first b9 = 1 Value 6.3 Request Start Of Frame The Start Of Frame (SOF) described in Figure 21 consists of: a falling edge, followed by ten Elementary Time Units (ETU) each containing a logical `0' followed by a single rising edge followed by two ETUs, each containing a logical `1'. Figure 21. Request Start Of Frame b0 ETU 0 b1 0 b2 0 b3 0 b4 0 b5 0 b6 0 b7 0 b8 0 b9 0 b10 1 b11 1 ai12050 27/46 6 CR14 ISO14443 type-B Radio Frequency data transfer CR14 6.4 Request End Of Frame The End Of Frame (EOF) shown in Figure 22 consists of: a falling edge, followed by ten Elementary Time Units (ETU) containing each a logical `0', followed by a single rising edge. Figure 22. Request End Of Frame b0 ETU 0 b1 0 b2 0 b3 0 b4 0 b5 0 b6 0 b7 0 b8 0 b9 0 ai09252 6.5 Input RF Data Transfer from the PICC to the CR14 (Answer Frame) The CR14 uses the ISO14443 type-B retro-modulation scheme which is demodulated and decoded by the RFIN circuitry. The modulation is obtained by modifying the PICC current consumption (load modulation). This load modulation induces an H-field variation, by coupling, that is detected by the CR14 RFIN input as a voltage variation on the antenna. The RFIN input demodulates this variation and decodes the information received from the PICC. Data must be transmitted using a 847kHz, BPSK modulated sub-carrier frequency, fS, as shown in Figure 23, and as specified in ISO14443 type-B. In BPSK, all data state transitions (from `0' to `1' or from `1' to `0') are encoded by phase shift keying the sub-carrier. Figure 23. Wave Received using BPSK Sub-carrier Modulation 1/106kHz PICC data bit to be transmitted to the CR14. 847kHz BPSK, resulting signal generated by the PICC for the load modulation. 1/847kHz phase shift VRFIN VRET Load modulation effect on the H-Field received on the CR14 RFIN input pad VDYN VOFFSET t ai12051 28/46 CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer 6.6 Transmission Format of Answer Frame Characters The PICC should use the same character format as that used for output data transfer (see Figure 20). An Answer Frame includes the SOF, data, CRC and the EOF, as illustrated in Figure 26. The data transfer rate is 106 kbit/s. The CR14 will also accept Answer Frames that do not contain the SOF and EOF delimiters, provided that these Frames are correctly set in the Parameter Register. (See Figure 26). 6.7 Answer Start Of Frame The PICC SOF must be compliant with the ISO14443 type-B, and is shown in Figure 24 Ten or eleven Elementary Time Units (ETU) each containing a logical `0', Two ETUs containing a logical `1'. Figure 24. Answer Start Of Frame b0 ETU 0 b1 0 b2 0 b3 0 b4 0 b5 0 b6 0 b7 0 b8 0 b9 0 b10 1 b11 1 b12 1 ai09254 6.8 Answer End Of Frame The PICC EOF must be compliant with the ISO14443 type-B, and is shown in Figure 25: Ten or eleven Elementary Time Units (ETU) each containing a logical `0', Two ETUs containing a logical `1' Figure 25. Answer End Of Frame b0 ETU 0 b1 0 b2 0 b3 0 b4 0 b5 0 b6 0 b7 0 b8 0 b9 0 b10 1 b11 1 b12 1 ai09254 29/46 6 CR14 ISO14443 type-B Radio Frequency data transfer CR14 6.9 Transmission Frame The Request Frame transmission must be followed by a minimum delay, t0 (see Table 13), in which no ASK or BPSK modulation occurs, before the Answer Frame can be transmitted. t0 is the minimum time required by the CR14 to switch from transmission mode to reception mode, and should be inserted after each frame. After t0, the 13.56MHz carrier frequency is modulated by the PICC at 847kHz for a minimum time of t1 (see Table 13) to allow the CR14 to synchronize. After t1, the first phase transition generated by the PICC represents the start bit (`0') of the Answer SOF (or the start bit `0' of the first data character in non SOF/EOF mode). Figure 26. Example of a Complete Transmission Frame Sent by the CR14 SOF 12 bits at 106Kb/s Cmd 10 bits Data 10 bits tDR fs = 847.5kHz Sync t0 64/fs Min t1 80/fs Min CRC 10 bits CRC 10 bits EOF 10 bits Case of Answer Frame with SOF & EOF Sent by the PICC SOF 12 or 13 bits Data 10 bits CRC 10 bits CRC 10 bits EOF 12 or 13 bits tWDG Sync Data 10 bits Data 10 bits Data 10 bits CRC 10 bits CRC 10 bits Case of Answer Frame without SOF & EOF t0 64/fs Min t1 80/fs Min tWDG Output Data Transfer using ASK Modulation Input Data Transfer using 847kHz BPSK Modulation ai12052 6.10 CRC The 16-bit CRC used by the CR14 follows the ISO14443 type B recommendation. For further information, please see Appendix A on page 44. The two CRC Bytes are present in all Request and Answer Frames, just before the EOF. The CRC is calculated on all the Bytes between the SOF and the CRC Bytes. Upon transmission of a Request from the CR14, the PICC verifies that the CRC value is valid. If it is invalid, it discards the frame and does not answer the CR14. Upon reception of an Answer from the PICC, the CR14 verifies that the CRC value is valid. If it is invalid, it stores the value FFh in the Input/Output Frame Register. The CRC is transmitted Least Significant Byte first. Each Byte is transmitted Least Significant Bit first. Figure 27. CRC Transmission Rules LSByte LSBit MSBit LSBit CRC 16 (8 bits) CRC 16 (8 bits) ai09256 MSByte MSBit 30/46 CR14 7 Tag access using the CR14 coupler 7 Tag access using the CR14 coupler In all the following IC commands, the last three bits of the Device Select Code can be replaced by any of the three-bit binary values (000, 001, 010, 011, 100, 101, 110, 111). These values are linked to the logic levels applied to the E2, E1 and E0 pads of the CR14. 7.1 Standard TAG Command Access Description Standard PICC commands, like Read and Write, are generated by the CR14 using the Input/ Output Frame Register. When the host needs to send a standard frame command to the PICC, it first has to internally generate the complete frame, with the command code followed by the command parameters. Only the two CRC Bytes should not be generated, as the CR14 automatically adds them during the RF transmission. When the frame is ready, the host has to write the request frame into the Input/Output Frame Register using the IC write command specified in Figure 13 on page 23. After the IC STOP condition, the CR14 inserts the IC Bytes in the required ISO character format ( Figure 20) and starts to transmit the request frame to the PICC. Once the RF transmission is over, the CR14 waits for the PICC to send an answer frame. If the PICC answers, the characters received (Figure 26) are demodulated, decoded and stored into the Input/Output Frame Register, as specified in Table 4. During the entire RF transmission, the CR14 disconnects itself from the IC bus. On reception of the PICC EOF, the CR14 checks the CRC and reconnects itself to the IC bus. The host can then get the PICC answer frame by issuing an Input/Output Frame Register Read on the IC bus, as specified in Figures 14 and 15. If no answer from the PICC is detected after a time-out delay, fixed in the Parameter Register (bits b5 and b6), the Input/Output Frame Register is set as specified in Table 4. Figure 28. Standard TAG Command: Request Frame Transmission S T A Device R Select T Code IC Input/ Output Register Address 01h Request Frame Length N TAG Cmd Code Data 1 Param Data 2 Param Data Param Data N S T O P CR14 SOF TAG Cmd Code Param Param Param CRC CRC SR14 EOF RF SOF Data 1 Data 2 Data Data N CRC CRC EOF ai12053 31/46 7 Tag access using the CR14 coupler CR14 Figure 29. Standard TAG Command: Answer Frame Reception TAG SOF IC TAG Data TAG Data TAG Data TAG Data TAG CRC TAG CRC TAG EOF S T A Device R Select T Code Input/ Output Register Address 01h Answer Frame Length P TAG Data Data 1 TAG Data Data 2 TAG Data Data TAG Data Data P S T O P RF SOF Data 1 Data 2 Data Data P CRC CRC EOF ai09261 Figure 30. Standard TAG Command: Complete TAG Access Description Device I/O Request Request Select Code Register Frame Frame Write Address Length Bytes STOP SOF RF Device Answer Request Select Frame Frame Code Length Bytes Read START EOF SOF EOF Request TAG Frame CRC T0 T1 Answer Frame CRC <--> <--> Characters Characters ai09262 IC START STOP 7.2 Anti-Collision TAG Sequence The CR14 can identify an ST short range memory using a proprietary anti-collision system. Issuing an IC Write command to the Slot Marker Register (Figure 16) causes the CR14 TO automatically generate a 16-slot anti-collision sequence, and to store the identified Chip_ID in the Input/Output Frame Register, as specified in Table 5. After receiving the Slot Marker Register IC Write command, the CR14 generates an RF PCALL16 command followed by fifteen SLOT_MARKER commands, from SLOT_MARKER(1) to SLOT_MARKER(15). After each command, the CR14 waits for a tag answer. If the answer is correctly decoded, the corresponding Chip_ID is stored in the Input/Output Frame Register. If there is no answer, or if the answer is wrong (with a CRC error, for example), the CR14 stores an error code in the Input/Output Frame Register. At the end of the sequence, the host has to read the Input/Output Frame Register to retrieve all the identified Chip_IDs. 32/46 CR14 Figure 31. Anti-Collision ST short range memory Sequence (1) S Slot T Device Marker S CR14 A Select Register T SOF R Code Address O P T IC 03h PCALL 16 TAG Command CRC CRC CR14 EOF TAG SOF 7 Tag access using the CR14 coupler TAG Chip_ID TAG CRC TAG CRC TAG EOF RF Slot 0 SOF 06h CR14 SOF 04h CRC CRC CRC EOF CR14 EOF t0 t1 <--> <--> SOF TAG SOF Chip_ID TAG Chip_ID CRC TAG CRC CRC TAG CRC EOF TAG EOF Slot Marker CRC Command IC RF... Slot 1 SOF 16h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 2 SOF 26h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 3 SOF 36h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 4 SOF 46h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 5 SOF 56h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 6 SOF 66h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 7 SOF 76h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 8 SOF 86h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF... Slot 9 SOF 96h CRC CRC EOF SOF Chip_ID CRC CRC EOF ai12054 t0 t1 <--> <--> 33/46 7 Tag access using the CR14 coupler CR14 Figure 32. Anti-Collision ST short range memory Sequence Continued IC RF ... Slot 10 SOF 96h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF ... Slot 11 SOF 56h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF ... Slot 12 SOF 66h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF ... Slot 13 SOF 76h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF ... Slot 14 SOF 86h CRC CRC EOF SOF Chip_ID CRC CRC EOF t0 t1 <--> <--> IC RF ... Slot 15 S T Device A Select R Code T SOF 96h CRC CRC EOF <--> <--> R E S T Device Answer Status Status Slot 1 I/O Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 0 Register A Select Frame Slot Bits Slot Bits Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Address R Code Length b0 to b7 b8 to b15 Answer Answer Answer Answer Answer Answer Answer Answer Answer T t0 t1 SOF Chip_ID CRC CRC EOF IC ... 01h 12h Status Status Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID RF S Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 T Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID O Answer Answer Answer Answer Answer Answer Answer P IC ... Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID RF ai09264 34/46 CR14 8 Maximum rating 8 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Symbol TSTG VIO VIO VCC POUT VESD Storage Temperature Input or Output range (SDA) Input or Output range (others pads) Supply Voltage Output Power on Antenna Output Driver (RFOUT) Electrostatic Discharge Voltage (Human Body model) (1) Electrostatic Discharge Voltage (Machine model) (2) Absolute Maximum Ratings Parameter Value -65 to 150 -0.3 to 6.5 -0.3 to Vcc+0.3 -0.3 to 6.5 100 4000 500 Unit C V V V mW V V 1. MIL-STD-883C, 3015.7 (100pF, 1500). 2. EIAJ IC-121 (Condition C) (200pF, 0) 35/46 9 DC and AC parameters CR14 9 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 9. IC AC Measurement Conditions Parameter VCC Supply Voltage Ambient Operating Temperature (TA) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 0.2VCC 0.3VCC Min. 4.5 -20 Max. 5.5 85 50 0.8VCC 0.7VCC Unit V C ns V V Figure 33. IC AC Testing I/O Waveform 0.8VCC 0.7VCC 0.3VCC AI09235 0.2VCC Table 10. Symbol CIN CIN tNS IC Input Parameters(1,2) Parameter Input Capacitance (SDA) Input Capacitance (SCL, E0, E1, E2)) Low Pass Filter Input Time Constant (SCL & SDA Inputs) 100 Test Condition Min. Max. 8 6 400 Unit pF pF ns 1. Sampled only, not 100% tested. 2. TA = 25 C, f = 400kHz. 36/46 CR14 Table 11. Symbol ILI ILO 9 DC and AC parameters IC DC Characteristics Parameter Test Condition 0V VIN VCC 0V VOUT VCC, SDA in Hi-Z VCC = 5V, fC = 400kHz (rise/fall time < 30ns), RF OFF Min. Max. 2 2 6 20 5 -0.3 -0.3 0.3VCC 0.3VCC Unit A A mA mA mA V V V V V Input Leakage Current (SCL, SDA, E0, E1, E2) Output Leakage Current (SCL, SDA, E0, E1, E2) ICC Supply Current VCC = 5V, fC = 400kHz (rise/fall time < 30ns), RF ON Supply Current (Stand-by) Input Low Voltage (SCL, SDA) Input Low Voltage (E0, E1, E2) Input High Voltage (SCL, SDA) Input High Voltage (E0, E1, E2) Output Low Voltage (SDA) IOL = 3mA, VCC = 5V VIN = VSS or VCC, VCC = 5V, RF OFF ICC1 VIL 0.7VCC VCC + 1 0.7VCC VCC + 1 0.4 VIH VOL 37/46 9 DC and AC parameters CR14 Figure 34. IC AC Waveforms tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH CLCH SCL tCLQV SDA OUT DATA VALID DATA OUTPUT tCLQX SCL tRFEX SDA IN tCHDH STOP CONDITION tCHDX CR14 command execution START CONDITION ai12055 38/46 CR14 Table 12. IC AC Characteristics Fast IC Symbol Alt. Parameter 400 kHz Min tCH1CH2(1) tCL1CL2(1) tDH1DH2(1) tDL1DL2(1) tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency 200 400 20 20 600 600 600 0 1.3 100 600 1.3 1000 Max 300 300 300 300 9 DC and AC parameters IC 100 kHz Min Max 1000 300 20 20 4700 4000 4000 0 4.7 250 4000 4.7 3500 200 100 1000 300 ns ns ns ns ns ns ns s s ns ns s ns ns kHz Unit 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle. 39/46 9 DC and AC parameters CR14 Figure 35. CR14 Synchronous Timing RFOUT ASK Modulated Signal VRFOUT tRFSBL tRFF A B tRFR tPOR fCC FRAME transmission between the reader and the contactless device tDR 1 0 tDR DATA 1 EOF FRAME transmitted by the CR14 in ASK FRAME transmitted by the PICC in BPSK t0 847kHz t1 SOF 1 1 0 DATA tDA tDA 1 0 DATA 10 Data jitter on FRAME transmitted by the CR14 in ASK tJIT 0 START tRFSBL tRFSBL tRFSBL tRFSBL ai12056 tJIT tJIT tJIT tJIT tRFSBL 40/46 CR14 Table 13. Symbol fCC MICARRIER tRFR, tRFF tRFSBL tJIT t0 t1 tWDG tWDG tWDG tWDG tDR PA tPOR 9 DC and AC parameters RFOUT AC Characteristics Parameter External Oscillator Frequency Carrier Modulation Index 10% Rise and Fall time Pulse Width on RFOUT ASK modulation bit jitter Antenna Reversal delay Synchronization delay Answer delay watchdog (b5=0, b6=0) Answer delay watchdog (b5=0, b6=1) Answer delay watchdog (b5=1, b6=0) Answer delay watchdog (b5=1, b6=1) Time Between Request characters RFOUT output power CR14 Power-On delay Condition VCC = 5V MI=(A-B)/(A+B) Min. 13.553 10 0.5 Max. 13.567 14 1.5 Unit MHz % s s 1 ETU = 128/fCC CR14 to PICC Min = 64/fS Min = 80/fS Request EOF rising edge to first Answer start bit CR14 to PICC 9.44 -0.5 75 94 500 5 10 309 9.44 90 20 0.5 s s s s ms ms ms s mW ms 1. Data specified in the table above are estimated or target values. All values can be updated during product qualification. Table 14. Symbol tRFSBL fS tDA VDYN VOFFSET VRET RFIN AC Characteristics Parameter PICC Pulse Width PICC Sub-carrier Frequency Time Between Answer characters RFIN Dynamic Voltage Level RFIN Offset Voltage Level RFIN Retro-modulation Level Condition 1 ETU = 128/fCC fCC/16 PICC to CR14 VDYN Max for VOFFSET = VCC/2 Min. Max. 9.44 847.5 1, 2, 3 0.5 2 120 VCC/2 3 Unit s KHz ETU V V mV 1. Data specified in the table above are estimated or target values. All values can be updated during product qualification. 41/46 10 Package mechanical CR14 10 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 36. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline A2 B e D A C CP N E 1 H A1 L SO-b 1. Drawing is not to scale. Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data millimeters inches Max. 1.75 0.10 0.25 1.60 0 0.35 0.19 8 0.46 0.25 0.10 9.80 1.27 - 3.80 0.40 16 10.00 - 4.00 1.27 0.050 0.386 - 0.150 0.016 16 0 0.014 0.007 0.004 Typ. Min. Max. 0.069 0.010 0.063 8 0.018 0.010 0.004 0.394 - 0.157 0.050 Symbol Typ. A A1 A2 a B C CP D e E L N Min. 42/46 CR14 11 Part numbering 11 Part numbering Table 16. Example: Ordering Information Scheme CR14 - MQ / XXX Device Type CR14 Package MQ = SO16 Narrow (150 mils width) MQP = SO16 Narrow (150 mils width) ECOPACK(R) Customer Code XXX = Given by the issuer For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 43/46 11 Part numbering CR14 Appendix A ISO14443 type B CRC calculation #include 44/46 CR14 12 Revision history 12 Revision history Table 17. Date 16-Dec-2005 Document Revision History Version 1 Initial release. Revision Details 45/46 CR14 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 46/46 |
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